1. Field of the Invention
The present invention relates to an apparatus and method for calculating a delay time it takes to transmit a signal from an input to an output of a logic functional block composed of MOS transistors.
2. Description of the Background Art
FIG. 4 is a block diagram of a conventional apparatus for calculating a delay time between logic functional blocks (hereinafter referred to as "macro cells"). As shown in FIG. 5, the apparatus calculates, between macro cells 21 and 22, a signal transmission delay time DT that is the time interval between the input of a signal S21 to the macro cell 21 and the output of a signal S22 (which is inputted to the macro cell 22) from the macro cell 21. With reference to FIG. 5, description will be given hereinafter on the delay time calculation apparatus of FIG. 4.
An RC lumped constant calculator 1 receives a layout pattern information D2 including the macro cells 21, 22 from a layout pattern storage file 2 and extracts an actual wiring length between the macro cells 21 and 22 from the layout pattern information D2. Taking the wiring between the macro cells 21 and 22 as a distributed constant line, the RC lumped constant calculator 1 calculates a resistance lumped constant R and a capacitance lumped constant C as RC lumped constants of an output-side (pin-side) wiring portion of the macro cell 21 from the actual wiring length between the macro cells 21 and 22.
A delay parameter retrieval portion 3 receives the layout pattern information D2 from the layout pattern storage file 2 and recognizes the type of the macro cell 21, to retrieve a fixed delay term K0 inherent in the macro cell 21 from a fixed delay information D4 stored in a delay information storage file 4.
An output impedance retrieval portion 5 receives the layout pattern information D2 from the layout pattern storage file 2 and recognizes the type of the macro cell 21, to retrieve a fixed output impedance RS0 inherent in the macro cell 21 from the fixed delay information D4 stored in the delay information storage file 4.
A delay time calculator 6 solves a predetermined delay calculation equation as a function of the parameters R, C, KO and RSO retrieved in the portions 1, 3 and 5, to calculate the delay time it takes to transmit the signal from the input to the output of the macro cell 21.
In the conventional delay time calculation apparatus thus constructed, the output impedance of the logic functional block (macro cell 21), which is one of the parameters for determining the delay time, is fixed in accordance with the type of logic functional block.
In practice, however, the output impedance and a fixed delay based on an output load of the macro cell 21 are not fixed. It is known that the output impedance of the macro cell, if composed of MOS transistors, is dependent on gate and drain voltages.
There has been a problem that the delay time is not calculated with high accuracy when the output impedance is fixed for each macro cell as seen in the prior art.
When the output impedance for each macro cell is subdivided in accordance with variations in gate and drain voltages for accurate calculation of the delay time in the conventional method, the capacitance to be stored in the fixed delay information file 4 greatly increases. This is not suitable for practical application.